1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to diode-based monolithic three-dimensional semiconductor memory.
2. Prior Arts
Three-dimensional memory (3D-M) is a monolithic semiconductor memory. It comprises a plurality of vertically stacked memory levels. As illustrated in FIG. 1, a 3D-M comprises at least a substrate level 30 and a memory level 40. The substrate level 30 comprises a plurality of transistors (38a . . . ). Formed in a single-crystalline semiconductor substrate 00, these transistors are single-crystalline transistors. Each transistor further includes a gate 34 and a source/drain 32. The memory level 40 comprises a plurality of address lines (42, 46 . . . ) and memory cells (48a . . . ). Each memory cell 48a is located at the cross-point between two address lines 42, 46. It comprises a thin-film diode 41 and a storage layer 43. The thin-film diode 41 prevents cross-talks between memory cells, while the storage layer 43 determines the data stored in the memory cell 48a. 
U.S. Pat. No. 7,386,652 issued to Zhang on Jun. 10, 2008, U.S. Pat. No. 7,423,304 issued to Cleeves et al on Sep. 9, 2008, and U.S. Pat. No. 7,728,391 issued to Zhang on Jun. 1, 2010 disclosed a small-pitch 3D-M (3D-MSP). The 3D-M in FIG. 1 is a 3D-MSP, where the minimum address-line pitch p of the memory level 40 (also referred to as the above-substrate pitch) is smaller than the minimum transistor-gate pitch P of the substrate level 30 (also referred to as the substrate pitch).
One factor that prior arts failed to notice is that the thin-film diode 41 in the 3D-M cell is a poly-crystalline diode which exhibits different electrical behavior than its single-crystalline counterpart. Here, a poly-crystalline diode is made of poly-crystalline material, e.g. poly-crystalline silicon (poly-Si). FIG. 1 further discloses a schematic drawing of the grain structure inside the thin-film diode 41 of the memory cell 48a. The dashed lines represent grain boundaries. When the 3D-MSP is scaled to the point where the size D of the thin-film diode 41 approaches the grain size G of poly-Si, more particularly when the critical dimension of the thin-film diode 41 is scaled to 40 nm or below, each thin-film diode 41 comprises just few crystalline grains: grains “a”, “b”, “c”, “d”, “e”. As a result, the thin-film diode 41 (i.e. memory cells) will exhibit significant performance variation: even two thin-film diodes with the same design (i.e. with same layout and cross-section) could have vastly different I-V characteristics. This leads to unacceptable read/write error rate. Furthermore, a large current fluctuation becomes more troublesome when multi-bit-per-cell is employed to increase the storage density of a 3D-MSP, because multi-bit-per-cell requires a tight current control.
In sum, the prior-art 3D-MSP has a poor performance and a limited storage density. To address these issues, the present invention discloses a small-grain 3D-M (3D-MSG).